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NXP Semiconductors /LPC18xx /SPIFI /CLIMIT

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Interpret as CLIMIT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLIMIT

Description

SPIFI cache limit register

Fields

CLIMIT

Zero-based upper limit of cacheable memory

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data